1. Field of the Invention
The present invention relates generally to the peak amplitude detection of high frequency signals and more particularly to a CMOS peak detector that does not require an off-chip peak storage capacitor.
2. Description of the Prior Art
Active peak detectors are used in applications which require the peak value of an input waveform to be determined or stored. Simple peak detectors may be constructed of a diode and a capacitor in which the highest value of the input signal charges the capacitor. There are several disadvantages to this simple set-up, including variable input impedance and temperature-induced diode drops. Another form of a peak detector employs operational amplifiers and feedback loops. The feedback, which is taken from the stored voltage at the capacitor, compensates for the diode drop. However, these circuits still suffer from variable input impedance problems.
Peak detectors known in the art are constructed using bipolar technology. One problem with bipolar technology is that it has a high rate of power dissipation. A bipolar peak detector also requires a high voltage supply (i.e., greater than 5 volts) to provide sufficient voltage swing through the diode, and hence, ensure linearity. Another problem with bipolar detectors is reverse leakage inherent in the diode which thereby sets the lower bound discharge rate of the capacitor. Furthermore, these peak detectors employ off-chip capacitors to store the peak amplitude. This additional circuitry adds significantly to cost and results in slightly less reliable performance.
Frequently, it is desired to step-down the stored peak amplitude in anticipation of receiving the next succeeding pulse. With respect to bipolar technology, discharging the storage capacitor involves either a large resistor or a current source tied to a DC voltage source. In the case of using the resistor, the amount of step-down must be fixed prior to circuit assembly (i.e., the desired step-down amount determines the value of the resistor). In both instances, the step-down results in a steady discharge of the storage capacitor from the instant the capacitor acquires the peak. Thus, succeeding circuit stages will not receive the true peak amplitude since a small amount will have already been discharged.
It would be advantageous if a peak detector could be implemented using CMOS technology and an on-chip storage capacitor, thereby decreasing overall power requirements and providing the ability to control the charge step-down on the storage capacitor. Another benefit could be realized if a single comparator could be used for multiple peak detectors.